This application claims the priority of Korean patent application Serial No. 99-61040 file on Dec. 23, 1999.
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and in particular to an improved method for fabricating a semiconductor device which can form a high integration MOSFET consisting of a gate electrode and source/drain regions.
2. Description of the Background Art
Recently, researches have been actively performed to miniaturize and functionalize a semiconductor device which has been widely employed for appliances, office devices and industrial systems.
It is essential to highly integrate a MISFET used as a unit constitutional element of the semiconductor device in order to achieve the miniaturization and functionalization of the semiconductor device.
A size of the MOSFET is dependent upon a critical dimension (CD) allowable error considering a minimum size of each pattern and pattern size variations in a mask process, and a misalignment allowable error considering misalignment between the patterns in the mask process.
On the other hand, in a conventional method for fabricating a semiconductor device, a gate electrode is partially overlapped with a device isolation insulation film, by considering the misalignment and CD variation in the mask process.
The conventional method for fabricating the semiconductor device will now be described with reference to FIG. 1.
FIG. 1 is a plan view illustrating major mask layers used to fabricate the semiconductor device.
As illustrated in FIG. 1, a gate electrode mask 104 is partially overlapped with a device isolation insulation film mask 102. Reference numeral 106 denotes a contact mask.
Here, an interval between adjacent MOSFETs corresponds to a sum of a minimum interval between the gate electrodes and an overlapped interval between the gate electrode and the device isolation insulation film.
For example, when the conventional method employs a design rule of 0.18 xcexcm, the minimum interval between the gate electrodes is 0.18 xcexcm.
In addition, the overlapped interval between the gate electrode and the device isolation insulation film is about 0.06 xcexcm when considering the misalignment and CD variation. Accordingly, the interval between the adjacent MOSFETs is a sum of the minimum interval between the gate electrodes and the overlapped interval between the gate electrode and the device isolation insulation film at both MOSFETs (0.18 xcexcm +0.6 xcexcm*2=0.30 xcexcm).
As described above, the conventional method for fabricating the semiconductor device has a disadvantage in that the overlapped interval between the gate electrode and the device isolation insulation film (0.06 xcexcm) is added to the both MOSFETs by considering the misalignment and CD variation in the mask process, and thus the size of the MOSFET is increased. As a result, it impedes the high integration of the MOSFET.
Accordingly, an object of the present invention is to provide a method for fabricating a semiconductor device which can achieve high integration of the semiconductor device by reducing a size of a MOSFET.
In order to achieve the above-described object of the present invention, a method for fabricating a semiconductor device includes the steps of: forming a device isolation insulation material, by forming a trench mask layer on a semiconductor substrate, forming a trench by partially etching the trench mask layer and the semiconductor substrate by employing a device isolation mask having a predetermined pattern, and filling up the trench; forming a device isolation insulation film on the trench, by exposing the upper portion of the trench mask layer by removing the device isolation insulation material according to an etch back process, forming a groove by removing a part of the device isolation insulation material in a presumed field region of a gate electrode line, and exposing a part of the semiconductor substrate by removing the trench mask layer; forming a gate insulation film on the exposed semiconductor substrate, and forming a conductive material for a gate electrode to fill up a stepped portion of the device isolation insulation film; and forming a gate electrode self aligned with the device isolation insulation film, by exposing the upper portion of the device isolation insulation film by removing the conductive material for the gate electrode according to an etch back process, and removing a part of the conductive material for the gate electrode according to an etching process using a gate electrode mask.
There is also provided a method for fabricating a semiconductor device, including the steps of: forming a device isolation insulation material, by sequentially forming a gate insulation material and a conductive material for a first gate electrode on a semiconductor substrate, forming a trench by partially etching the conductive material for the first gate electrode, the gate insulation material and the semiconductor substrate by employing a device isolation mask having a predetermined pattern, and filling up the trench; forming a groove, by exposing the upper portion of the conductive material for the first gate electrode by removing the device isolation insulation material according to an etch back process, and removing a part of the device isolation insulation material in a presumed field region of a gate electrode line; forming a conductive material for a gate electrode, by forming a conductive material for a second gate electrode to fill up the groove, and exposing the upper portions of the device isolation insulation material and the conductive material for the first gate electrode by removing the conductive material for the second gate electrode according to an etch back process; and forming a gate electrode self aligned with the device isolation insulation film, by removing a part of the conductive material for the gate electrode according to an etching process using a gate electrode mask having a predetermined pattern.